Jobs filters

ADVANCED SOFTWARE ENGINEER(SEMICONDUCTOR DIGITAL TWIN RND) - EDA - 492077
Hsinchu City, Taiwan
APPLICATION SUPPORT ENGINEER - VERIFICATION - 492268
Hsinchu City, Taiwan
SOFTWARE ENGINEER(SEMICONDUCTOR DIGITAL TWIN RND) - 492078
Hsinchu City, Taiwan
SOFTWARE ENGINEER(SEMICONDUCTOR DIGITAL TWIN RND) - 492079
Hsinchu City, Taiwan
ASSOCIATE PRINCIPAL PRODUCT ENGINEER(APRISA) - 493252
Taipei City, Taiwan
PRODUCT ENGINEER(APRISA 3DIC) - 493292
Taipei City, Taiwan
SENIOR APPLICATION SUPPORT ENGINEER - 493198
Taipei City, Taiwan
APPLICATION ENGINEER (VELOCE EMULATION) - 465973
Shanghai, China
SENIOR SOFTWARE DEVELOPMENT ENGINEER-CAL DRC TWN - 485960
Hsinchu City, Taiwan
SOFTWARE ENGINEER – SENIOR CAL DRC TWN - 485963
Hsinchu City, Taiwan
SENIOR PRODUCT ENGINEER (CALIBRE DRC) - 485445
Hsinchu City, Taiwan
SENIOR SW QA ENGINEER (DRC) - 485447
Hsinchu City, Taiwan
ASSOCIATE PRINCIPAL PRODUCT ENGINEER(APRISA) - 493252
Taipei City, TaiwanSiemens Digital Industries Software is driving transformation to enable a digital enterprise where engineering, manufacturing and electronics design meet tomorrow. Our solutions help companies of all sizes create and leverage digital twins that provide organizations with new insights, opportunities and levels of automation to drive innovation.
Siemens EDA seeks a highly motivated engineer with the capability and desire to make a meaningful contribution to the IC design and manufacturing industry. This Product Engineer position at Siemens EDA/Taiwan plays a meaningful role in the success of Siemens's customers as they craft the state-of-the-art IC products. This person will work with semiconductor foundries and R&D to tackle technical challenges in the areas of 3DIC related area.
Location: TPE or Hsinchu
Job Role:
• Working on 7nm, 5nm and 4nm designs with various customers for deployment of Aprisa place and route tools.
• Responsible for defining and working on 3DIC flow with Aprisa tools
• Closely working with Foundry and early customers on adoption of the 3DIC flow.
Job Requirement:
• Typically requires minimum of 5-15 years of experience in Physical Design with mainstream P&R tools
• Should have worked on 3DIC designs or flow/methodology development
• Hands on experience with 3DIC compiler or integrity tool
• Hands on experience in Physical Design (floorplan, placement, CTS and routing) and timing closure of complex blocks and/or Full Chip designs.
• Hands-on experience with commercial place & route tools like Synopsys-lCC2, Cadence-lnnovus or Aprisa is a must.
• Tapeout experience of 2 or more projects is a must.
• Good understanding of timing, power and area trade-offs.
• Ability to pickup new flows, learn on the job and influence QOR is a must.
• Experience delivering designs with multiple voltage islands and top-level floorplanning & chip-assembly is a plus.
• TCL, Perl or Python scripting is a plus.
• Strong verbal and written communication skills; good presentation skills
• Good problem solving and debugging skills #Li-EDA#LI-onsite#Li-ML7
A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we welcome applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit, and business need. Bring your curiosity and creativity and help us shape tomorrow!
We offer a comprehensive reward package which includes a competitive basic salary, bonus scheme, generous holiday allowance, pension, and private healthcare.
Siemens Software. Where today meets tomorrow.
We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status.
Location: TPE or Hsinchu
Job Role:
• Working on 7nm, 5nm and 4nm designs with various customers for deployment of Aprisa place and route tools.
• Responsible for defining and working on 3DIC flow with Aprisa tools
• Closely working with Foundry and early customers on adoption of the 3DIC flow.
Job Requirement:
• Typically requires minimum of 5-15 years of experience in Physical Design with mainstream P&R tools
• Should have worked on 3DIC designs or flow/methodology development
• Hands on experience with 3DIC compiler or integrity tool
• Hands on experience in Physical Design (floorplan, placement, CTS and routing) and timing closure of complex blocks and/or Full Chip designs.
• Hands-on experience with commercial place & route tools like Synopsys-lCC2, Cadence-lnnovus or Aprisa is a must.
• Tapeout experience of 2 or more projects is a must.
• Good understanding of timing, power and area trade-offs.
• Ability to pickup new flows, learn on the job and influence QOR is a must.
• Experience delivering designs with multiple voltage islands and top-level floorplanning & chip-assembly is a plus.
• TCL, Perl or Python scripting is a plus.
• Strong verbal and written communication skills; good presentation skills
• Good problem solving and debugging skills #Li-EDA#LI-onsite#Li-ML7
A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we welcome applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit, and business need. Bring your curiosity and creativity and help us shape tomorrow!
We offer a comprehensive reward package which includes a competitive basic salary, bonus scheme, generous holiday allowance, pension, and private healthcare.
Siemens Software. Where today meets tomorrow.
We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status.




