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SENIOR DESIGN VERIFICATION ENGINEER - 437651
El Qahera El Gididaa, EGYSiemens Digital Industries Software is driving transformation to enable a digital enterprise where engineering, manufacturing and electronics design meet tomorrow. Our solutions help companies of all sizes create and leverage digital twins that provide organizations with new insights, opportunities and levels of automation to drive innovation.
Siemens Digital Industries Software is a global technology powerhouse. With some of the best-known brands in the world, Siemens has stood for engineering excellence, innovation, quality, and reliability for more than 175 years.
We're looking for a Senior Design Verification Engineer to join our Storage Solutions R&D team in Cairo, Egypt.
Responsibilities:
- Develop and execute verification plans, including testbench architecture and test case development.
- Design and implement simulation or co-emulation-based verification environments.
- Work on complex, existing testbenches targeting various platforms (simulation/co-emulation).
- Integrate Software and Hardware DUTs with verification environments and handle diverse programming tasks.
- Implement and monitor code and functional coverage metrics to assess verification completeness.
- Run and debug testbenches composed of embedded software and hardware components on platforms such as Questa or Veloce.
- Collaborate with design and architecture teams to understand design specifications and requirements.
- Identify, debug, and resolve issues in both the design and verification environment.
- Work with the design team to close any coverage gaps.
- Mentor junior engineers and promote best practices in verification.
- Document and report verification progress and coverage status to stakeholders.
Job Requirements:
- B.Sc. or M.Sc. in Computer, Electronics, or Communication Engineering.
- Proven experience in H/W design verification.
- Expertise in SystemVerilog for creating testbenches and writing assertions.
- Proficient in UVM (Universal Verification Methodology) for building reusable verification environments.
- Strong understanding of code coverage and functional coverage techniques.
- Experience with integrating commercial VIP into UVM testbenches.
- Solid knowledge of RTL development and Verilog.
- Strong understanding of digital circuits, design, and computer architecture.
- Familiarity with Siemens EDA tools and solutions.
- Knowledge of C, C++, and object-oriented programming.
- Proficiency in scripting languages (Perl, Shell, TCL).
- Excellent command of the English language, with strong presentation and communication skills.
- Ability to work independently and collaboratively in a team environment.
- Knowledge of storage protocol standards (UFS, USB, SAS, SATA, etc.) is a plus.
- Experience with SystemC programming is a plus.
We’re Siemens. A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we welcome applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow!
We offer a comprehensive reward package which includes a competitive basic salary, bonus scheme and generous holiday allowance.
Siemens is an equal opportunities employer and do not discriminate unlawfully on any grounds. We are committed to providing access and equal opportunity.
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